Verisity and 0-In Collaborate for Integrated Testbench and Assertion Coverage Metrics

Design Automation Conference 2003

Single Interface to Be Shown at DAC 2003 Provides Comprehensive View of Verification Thoroughness

Advanced testbenches and assertion-based verification (ABV) are complementary approaches

"Many of the world's largest and most sophisticated semiconductor designs rely on Verisity's products for system-level verification," said Moshe Gavrielov, chief executive officer at Verisity. "Specman Elite is the industry-leading testbench automation solution and many of our customers are choosing to supplement their Specman Elite environments by adding assertions to check their internal design structures. 0-In is a leader in assertion-based verification, which is entirely complementary to our products. This joint solution delivers an integrated, best-in-class verification solution for our mutual customers."

"Assertions are statements of design intent that are leveraged by simulation, formal verification and hardware acceleration/emulation to ensure that the design behaves as intended," added 0-In president and CEO Emil Girczyc. "Our new unified verification coverage methodology provides an automated metric that directly links assertions, simulation, and formal verification to speed verification of system-on-chip and ASIC designs. Many of our customers use Specman Elite to drive their testbenches and this solution responds to their need for a single view of verification from best-in-class tools rather than the 'one size fits all' perspective of some other verification tool vendors."

"Combined coverage metrics from the Verisity and 0-In tools will be of great benefit to our projects," commented Kevin Jones, verification manager at Rambus Inc. "We have found Specman Elite and 0-In's assertions to be useful and complementary for our most complex designs. We encouraged the two companies to work together on integrated coverage and are glad to see this solution. It will allow us to focus our verification efforts on areas of the design that are not well exercised, speeding up our development process and increasing our confidence that all bugs are found before tape-out."

Comprehensive coverage view available in the Specman Elite environment

Specman Elite offers a comprehensive environment for all aspects of verification, including automatic generation of functional tests, data and assertion checking, and functional coverage analysis. Specman Elite's functional coverage GUI provides a wide range of metrics based upon how well the testbench has exercised the functionality of a chip design. In addition, the metrics from Verisity's SureCov(TM) code coverage tool are available, including block, arc, toggle and expression coverage. With the new integration, structural coverage from 0-In's CheckerWare library will also be viewable within Specman Elite. In related news, Verisity also announced today a new coverage assertion interface (CAI) to Specman Elite that provides a heterogeneous view of functional, code and structural coverage metrics. (see related release, "Verisity Increases Support for Open Standards," dated June 2, 2003). The integration between Specman Elite and 0-in's CheckerWare was developed using CAI.

The 0-In assertion checkers provide structural coverage showing which corner-case conditions have been exercised during simulation and formal verification. Examples of these conditions include a FIFO reaching its empty and full states, all the requests to an arbiter being exercised, and a multi-cycle window hitting both its minimum and maximum durations. 0-In's CheckerWare monitors check industry-standard buses and interfaces, providing structural coverage information on whether all of the legal transaction types have been tried. CheckerWare monitors are available for more than 20 standards, including PCI, PCI Express, UTOPIA, SPI4-2, HyperTransport and InfiniBand.

With this new joint effort from Verisity and 0-In, Specman Elite provides a unique view of verification thoroughness metrics for both simulation and formal verification, encompassing code coverage, functional coverage and structural coverage.

Integrated coverage metrics foster coverage-driven verification

One very important aspect of complex chip functional verification is the use of coverage metrics to identify next steps at each stage of the verification process. This leads to coverage-driven verification, in which verification "holes" are identified from the coverage metrics and then improvements in the metrics gauge the effectiveness of additional effort. Within a Specman Elite-based verification flow, users can examine all forms of coverage metrics to assess areas of functionality not sufficiently exercised, adapt the constraints for pseudo-random test generation to exercise these areas, and then validate the effect by looking at the revised metrics.

Within the 0-In verification flow, the structural coverage metric plays three roles. The metric helps the users identify verification hot spots, exercise these hot spots in simulation and measure the results, and confirm that the hot spots are fully verified with formal methods. The combined capabilities of the Verisity and 0-In tools allow users to measure whether there are enough assertions in the design, how well the design is exercised in simulation and how much additional confirmation has been provided by formal verification.

Verisity and 0-In to demonstrate new capability at DAC

Visitors to the upcoming Design Automation Conference (DAC), June 2-5 in Anaheim, Calif., will be able to view the integrated coverage metrics at both the Verisity booth (number 2210) and at the 0-In booth (number 1056). The capability will be available to joint customers in Q3, 2003.

About Verisity

Verisity, Ltd. (Nasdaq:VRST) is the leading supplier of essential technology and methodology for the functional verification market. The company addresses customers' critical business issues with its market-leading software and intellectual property (IP) that effectively and efficiently verify the design of electronic systems and complex integrated circuits for the communications, computing, and consumer electronics global markets. Verisity's Specman Elite(R) testbench automation solution automates manual processes and detects critical flaws in hardware designs enabling delivery of the highest quality products and accelerating time to market. The company's strong market presence is driven by its proven technology, methodology, and solid strategic partnerships and programs. Verisity's customer list includes leading companies in all strategic technology sectors. Verisity is a global organization with offices throughout Asia, Europe, and North America. Verisity's principal executive offices are located in Mountain View, California, with its principal research and development offices located in Rosh Ha'ain, Israel. For more information, visit www.verisity.com.

About 0-In

0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle -- from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

Note to Editors: Verisity, the Verisity logo and Specman Elite are either registered trademarks or trademarks of Verisity Design, Inc. in the United States and/or other jurisdictions. 0-In(R) and CheckerWare(R) are registered trademarks of 0-In Design Automation, Inc. All other trademarks are the property of their respective holders.

CONTACT: Verisity Design, Inc.
             Jennifer Bilsey, 650/934-6823
             jen@verisity.com
              or
             0-In Design Automation
             Steve White, 408/487-3649
             swhite@0-in.com
              or
             Cayenne Communication for 0-In Design Automation
             Linda Marchant, 919/683-9545
             linda.marchant@cayennecom.com